View SST39VF3201C_4781239.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

a microchip technology company ?2011 silicon storage technology, inc. ds25020a 06/11 preliminary specifications www.microchip.com 32 mbit (x16) multi-purpose flash plus SST39VF3201C / sst39vf3202c features ? organized as 2m x16 ? single voltage read and write operations ? 2.7-3.6v ? superior reliability ? endurance: 100,000 cycles (typical) ? greater than 100 years data retention ? low power consumption (typical values at 5 mhz) ? active current: 6 ma (typical) ? standby current: 4 a (typical) ? auto low power mode: 4 a (typical) ? hardware block-protection/wp# input pin ? top block-protection (top two 4-kword blocks) for sst39vf3202c ? bottom block-protection (bottom two 4-kword blocks) for SST39VF3201C ? sector-erase capability ? uniform 2 kword sectors ? block-erase capability ? flexible block architecture ? eight 4-kword blocks, 63 32-kword blocks ? chip-erase capability ? erase-suspend/erase-resume capabilities ? hardware reset pin (rst#) ? security-id feature ? sst: 128 bits; user: 128 words ? fast read access time: ?70ns ? latched address and data ? fast erase and word-program: ? sector-erase time: 18 ms (typical) ? block-erase time: 18 ms (typical) ? chip-erase time: 35 ms (typical) ? word-program time: 7 s (typical) ? automatic write timing ? internal v pp generation ? end-of-write detection ? toggle bits ? data# polling ? ry/by# pin ? cmos i/o compatibility ? jedec standard ? flash eeprom pin assignments ? packages available ? 48-lead tsop (12mm x 20mm) ? 48-ball tfbga (6mm x 8mm) ? all devices are rohs compliant the SST39VF3201C and sst39vf3202c devices are 2m x16, cmos multi-pur- pose flash plus (mpf+) manufactured with sst's proprietary, high performance cmos superflash technology. the split-gate cell design and thick-oxide tunnel- ing injector attain better reliability and manufacturability compared with alternate approaches. the SST39VF3201C and sst39vf3202c write (program or erase) with a 2.7-3.6v power supply. this device conforms to jedec standard pinouts for x16 memories.
?2011 silicon storage technology, inc. ds25020a 06/11 2 32 mbit multi-purpose flash plus SST39VF3201C / sst39vf3202c preliminary specifications a microchip technology company product description the SST39VF3201C and sst39vf3202c devices are 2m x16 cmos multi-purpose flash plus (mpf+) manufactured with sst?s proprietary, high-performance cmos superflash technology. the split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. the SST39VF3201C/3202c write (program or erase) with a 2.7- 3.6v power supply. these devices conform to jedec standard pin assignments for x16 memories. featuring high performance word-program, the SST39VF3201C/3202c devices provide a typical word-program time of 7 sec. these devices use toggle bit, data# polling, or ry/by# pin to indicate the completion of program operation. to protect against inadvertent write, they have on-chip hardware and software data protection schemes. designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with a guaranteed typical endurance of 100,000 cycles. data retention is rated at greater than 100 years. the SST39VF3201C/3202c devices are suited for applications that require convenient and economical updating of program, configuration, or data memory. for all system applications, they significantly improve performance and reliability, while lowering power consumption. they inherently use less energy during erase and program than alternative flash technologies. the total energy consumed is a function of the applied voltage, current, and time of application. since for any given voltage range, the superflash technology uses less current to program and has a shorter erase time, the total energy consumed during any erase or program operation is less than alternative flash technologies. these devices also improve flexibility while lowering the cost for program, data, and configuration storage applications. the superflash technology provides fixed erase and program times, independent of the number of erase/program cycles that have occurred. therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose erase and pro- gram times increase with accumulated erase/program cycles. to meet high-density, surface mount requirements, the SST39VF3201C/3202c devices are offered in 48-lead tsop and 48-ball tfbga packages. see figure 2 and figure 3 for pin assignments.
?2011 silicon storage technology, inc. ds25020a 06/11 3 32 mbit multi-purpose flash plus SST39VF3201C / sst39vf3202c preliminary specifications a microchip technology company block diagram figure 1: functional block diagram y-decoder i/o buffers and data latches 1410 b1.0 address buffer latches x-decoder dq 15 -dq 0 memory address oe# ce# we# superflash memory control logic wp# reset# ry/by#
?2011 silicon storage technology, inc. ds25020a 06/11 4 32 mbit multi-purpose flash plus SST39VF3201C / sst39vf3202c preliminary specifications a microchip technology company pin assignments figure 2: pin assignments for 48-lead tsop figure 3: pin assignments for 48-ball tfbga a15 a14 a13 a12 a11 a10 a9 a8 a19 a20 we# rst# nc wp# ry/by# a18 a17 a7 a6 a5 a4 a3 a2 a1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 a16 nc v ss dq15 dq7 dq14 dq6 dq13 dq5 dq12 dq4 v dd dq11 dq3 dq10 dq2 dq9 dq1 dq8 dq0 oe# v ss ce# a0 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1410 48-tsop ek p1.0 standard pinout top view die up 1410 4-tfbga b1k p2.0 abcdefgh 6 5 4 3 2 1 top view (balls facing down) a13 a9 we# ry/by# a7 a3 a12 a8 rst# wp# a17 a4 a14 a10 nc a18 a6 a2 a15 a11 a19 a20 a5 a1 a16 dq7 dq5 dq2 dq0 a0 nc dq14 dq12 dq10 dq8 ce# dq15 dq13 v dd dq11 dq9 oe# v ss dq6 dq4 dq3 dq1 v ss
?2011 silicon storage technology, inc. ds25020a 06/11 5 32 mbit multi-purpose flash plus SST39VF3201C / sst39vf3202c preliminary specifications a microchip technology company table 1: pin description symbol pin name functions a ms 1 -a 0 1. a ms = most significant address a ms =a 20 for SST39VF3201C/3202c address inputs to provide memory addresses. during sector-erase a ms -a 11 address lines will select the sector. during block-erase a ms -a 15 address lines will select the block. dq 15 -dq 0 data input/output to output data during read cycles and receive input data during write cycles. data is internally latched during a write cycle. the outputs are in tri-state when oe# or ce# is high. wp# write protect to protect the top/bottom boot block from erase/program operation when grounded. rst# reset to reset and return the device to read mode. ce# chip enable to activate the device when ce# is low. oe# output enable to gate the data output buffers. we# write enable to control the write operations. v dd power supply to provide power supply voltage: 2.7-3.6v v ss ground nc no connection unconnected pins. ry/by# ready/busy# to output the status of a program or erase operation ry/by# is a open drain output, so a 10k ? - 100k ? pull-up resistor is required to allow ry/by# to transition high indicating the device is ready to read. t1.0 25020
?2011 silicon storage technology, inc. ds25020a 06/11 6 32 mbit multi-purpose flash plus SST39VF3201C / sst39vf3202c preliminary specifications a microchip technology company table 2: top / bottom boot block address (1 of 2) top boot block address sst39vf3202c bottom boot block address SST39VF3201C # size (kword) address range # size (kword) address range 70 4 1ff000h-1fffffh 70 32 1f8000h-1fffffh 69 4 1fe000h-1fefffh 69 32 1f0000h-1f7fffh 68 4 1fd000h-1fdfffh 68 32 1e8000h-1effffh 67 4 1fc000h-1fcfffh 67 32 1e0000h-1e7fffh 66 4 1fb000h-1fbfffh 66 32 1d8000h-1dffffh 65 4 1fa000h-1fafffh 65 32 1d0000h-1d7fffh 64 4 1f9000h-1f9fffh 64 32 1c8000h-1cffffh 63 4 1f8000h-1f8fffh 63 32 1c0000h-1c7fffh 62 32 1f0000h-1f7fffh 62 32 1b8000h-1bffffh 61 32 1e8000h-1effffh 61 32 1b0000h-1b7fffh 60 32 1e0000h-1e7fffh 60 32 1a8000h-1affffh 59 32 1d8000h-1dffffh 59 32 1a0000h-1a7fffh 58 32 1d0000h-1d7fffh 58 32 198000h-19ffffh 57 32 1c8000h-1cffffh 57 32 190000h-197fffh 56 32 1c0000h-1c7fffh 56 32 188000h-18ffffh 55 32 1b8000h-1bffffh 55 32 180000h-187fffh 54 32 1b0000h-1b7fffh 54 32 178000h-17ffffh 53 32 1a8000h-1affffh 53 32 170000h-177fffh 52 32 1a0000h-1a7fffh 52 32 168000h-16ffffh 51 32 198000h-19ffffh 51 32 160000h-167fffh 50 32 190000h-197fffh 50 32 158000h-15ffffh 49 32 188000h-18ffffh 49 32 150000h-157fffh 48 32 180000h-187fffh 48 32 148000h-14ffffh 47 32 178000h-17ffffh 47 32 140000h-147fffh 46 32 170000h-177fffh 46 32 138000h-13ffffh 45 32 168000h-16ffffh 45 32 130000h-137fffh 44 32 160000h-167fffh 44 32 128000h-12ffffh 43 32 158000h-15ffffh 43 32 120000h-127fffh 42 32 150000h-157fffh 42 32 118000h-11ffffh 41 32 148000h-14ffffh 41 32 110000h-117fffh 40 32 140000h-147fffh 40 32 108000h-10ffffh 39 32 138000h-13ffffh 39 32 100000h-107fffh 38 32 130000h-137fffh 38 32 0f8000h-0fffffh 37 32 128000h-12ffffh 37 32 0f0000h-0f7fffh 36 32 120000h-127fffh 36 32 0e8000h-0effffh 35 32 118000h-11ffffh 35 32 0e0000h-0e7fffh 34 32 110000h-117fffh 34 32 0d8000h-0dffffh 33 32 108000h-10ffffh 33 32 0d0000h-0d7fffh 32 32 100000h-107fffh 32 32 0c8000h-0cffffh 31 32 0f8000h-0fffffh 31 32 0c0000h-0c7fffh
?2011 silicon storage technology, inc. ds25020a 06/11 7 32 mbit multi-purpose flash plus SST39VF3201C / sst39vf3202c preliminary specifications a microchip technology company 30 32 0f0000h-0f7fffh 30 32 0b8000h-0bffffh 29 32 0e8000h-0effffh 29 32 0b0000h-0b7fffh 28 32 0e0000h-0e7fffh 28 32 0a8000h-0affffh 27 32 0d8000h-0dffffh 27 32 0a0000h-0a7fffh 26 32 0d0000h-0d7fffh 26 32 098000h-09ffffh 25 32 0c8000h-0cffffh 25 32 090000h-097fffh 24 32 0c0000h-0c7fffh 24 32 088000h-08ffffh 23 32 0b8000h-0bffffh 23 32 080000h-087fffh 22 32 0b0000h-0b7fffh 22 32 078000h-07ffffh 21 32 0a8000h-0affffh 21 32 070000h-077fffh 20 32 0a0000h-0a7fffh 20 32 068000h-06ffffh 19 32 098000h-09ffffh 19 32 060000h-067fffh 18 32 090000h-097fffh 18 32 058000h-05ffffh 17 32 088000h-08ffffh 17 32 050000h-057fffh 16 32 080000h-087fffh 16 32 048000h-04ffffh 15 32 078000h-07ffffh 15 32 040000h-047fffh 14 32 070000h-077fffh 14 32 038000h-03ffffh 13 32 068000h-06ffffh 13 32 030000h-037fffh 12 32 060000h-067fffh 12 32 028000h-02ffffh 11 32 058000h-05ffffh 11 32 020000h-027fffh 10 32 050000h-057fffh 10 32 018000h-01ffffh 9 32 048000h-04ffffh 9 32 010000h-017fffh 8 32 040000h-047fffh 8 32 008000h-00ffffh 7 32 038000h-03ffffh 7 4 007000h-007fffh 6 32 030000h-037fffh 6 4 006000h-006fffh 5 32 028000h-02ffffh 5 4 005000h-005fffh 4 32 020000h-027fffh 4 4 004000h-004fffh 3 32 018000h-01ffffh 3 4 003000h-003fffh 2 32 010000h-017fffh 2 4 002000h-002fffh 1 32 008000h-00ffffh 1 4 001000h-001fffh 0 32 000000h-007fffh 0 4 000000h-000fffh t2.25020 table 2: top / bottom boot block address (continued) (2 of 2)
?2011 silicon storage technology, inc. ds25020a 06/11 8 32 mbit multi-purpose flash plus SST39VF3201C / sst39vf3202c preliminary specifications a microchip technology company device operation commands are used to initiate the memory operation functions of the device. commands are written to the device using standard microprocessor write sequences. a command is written by asserting we# low while keeping ce# low. the address bus is latched on the falling edge of we# or ce#, whichever occurs last. the data bus is latched on the rising edge of we# or ce#, whichever occurs first. the SST39VF3201C/3202c also have the auto low power mode which puts the device in a near standby mode after data has been accessed with a valid read operation. this reduces the i dd active read current from typically 9 ma to typically 4 a. the auto low power mode reduces the typical i dd active read current to the range of 2 ma/mhz of read cycle time. the device exits the auto low power mode with any address transition or control signal transition used to initiate another read cycle, with no access time penalty. note that the device does not enter auto-low power mode after power-up with ce# held steadily low, until the first address transition or ce# is driven high. read the read operation of the SST39VF3201C/3202c is controlled by ce# and oe#, both have to be low for the system to obtain data from the outputs. ce# is used for device selection. when ce# is high, the chip is deselected and only standby power is consumed. oe# is the output control and is used to gate data from the output pins. the data bus is in high impedance state when either ce# or oe# is high. refer to the read cycle timing diagram for further details (figure 5). word-program operation the SST39VF3201C/3202c are programmed on a word-by-word basis. before programming, the sector where the word exists must be fully erased. the program operation is accomplished in three steps. the first step is the three-byte load sequence for software data protection. the second step is to load word address and word data. during the word-program operation, the addresses are latched on the falling edge of either ce# or we#, whichever occurs last. the data is latched on the rising edge of either ce# or we#, whichever occurs first. the third step is the internal program operation which is ini- tiated after the rising edge of the fourth we# or ce#, whichever occurs first. the program operation, once initiated, will be completed within 10 s. see figure 6 and figure 7 for we# and ce# controlled program operation timing diagrams and figure 21 for flowcharts. during the program operation, the only valid reads are data# polling and toggle bit. during the internal program operation, the host is free to perform additional tasks. any commands issued during the internal program operation are ignored. during the command sequence, wp# should be statically held high or low. sector/block-erase operation the sector- (or block-) erase operation allows the system to erase the device on a sector-by-sector (or block-by-block) basis. the SST39VF3201C/3202c offer both sector-erase and block-erase mode. the sector architecture is based on uniform sector size of 2 kword. the block-erase mode is based on block sizes of 4 and 32 kword. the sector-erase operation is initiated by executing a six-byte com- mand sequence with sector-erase command (50h) and sector address (sa) in the last bus cycle. the block-erase operation is initiated by executing a six-byte command sequence with block-erase com- mand (30h) and block address (ba) in the last bus cycle. the sector or block address is latched on the falling edge of the sixth we# pulse, while the command (50h or 30h) is latched on the rising edge of the sixth we# pulse. the internal erase operation begins after the sixth we# pulse. the end-of-erase operation can be determined using either data# polling or toggle bit methods. see figure 11 and fig-
?2011 silicon storage technology, inc. ds25020a 06/11 9 32 mbit multi-purpose flash plus SST39VF3201C / sst39vf3202c preliminary specifications a microchip technology company ure 12 for timing waveforms and figure 25 for the flowchart. any commands issued during the sector- or block-erase operation are ignored. when wp# is low, any attempt to sector- (block-) erase the pro- tected block will be ignored. during the command sequence, wp# should be statically held high or low. erase-suspend/erase-resume commands the erase-suspend operation temporarily suspends a sector- or block-erase operation thus allowing data to be read from any memory location, or program data into any sector/block that is not suspended for an erase operation. the operation is executed by issuing one byte command sequence with erase- suspend command (b0h). the device automatically enters read mode typically within 10 s after the erase-suspend command had been issued. valid data can be read from any sector or block that is not suspended from an erase operation. reading at address location within erase-suspended sectors/ blocks will output dq 2 toggling and dq 6 at ?1?. while in erase-suspend mode, a word-program opera- tion is allowed except for the sector or block selected for erase-suspend. to resume sector-erase or block-erase operation which has been suspended the system must issue erase resume command. the operation is executed by issuing one byte command sequence with erase resume command (30h) at any address in the last byte sequence. chip-erase operation the SST39VF3201C/3202c provide a chip-erase operation, which allows the user to erase the entire memory array to the ?1? state. this is useful when the entire device must be quickly erased. the chip-erase operation is initiated by executing a six-byte command sequence with chip-erase command (10h) at address 555h in the last byte sequence. the erase operation begins with the rising edge of the sixth we# or ce#, whichever occurs first. during the erase operation, the only valid read is toggle bit or data# polling. see table 7 for the command sequence, figure 10 for timing diagram, and figure 25 for the flowchart. any commands issued during the chip-erase operation are ignored. when wp# is low, any attempt to chip-erase will be ignored. during the command sequence, wp# should be statically held high or low. write operation status detection the SST39VF3201C/3202c pro vide two software means to detect the completion of a write (program or erase) cycle, in order to optimize the system write cycle time. the software detection includes two status bits: data# polling (dq 7 ) and toggle bit (dq 6 ). the end-of-write detection mode is enabled after the rising edge of we#, which initiates the internal program or erase operation. the actual completion of the nonvolatile write is asynchronous with the system; therefore, either a data# polling or toggle bit read may be simultaneous with the completion of the write cycle. if this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either dq 7 or dq 6 . in order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. if both reads are valid, then the device has completed the write cycle, otherwise the rejection is valid.
?2011 silicon storage technology, inc. ds25020a 06/11 10 32 mbit multi-purpose flash plus SST39VF3201C / sst39vf3202c preliminary specifications a microchip technology company data# polling (dq 7 ) when the SST39VF3201C/3202c are in the internal program operation, any attempt to read dq 7 will produce the complement of the true data. once the program operation is completed, dq 7 will produce true data. note that even though dq 7 may have valid data immediately following the completion of an internal write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive read cycles after an interval of 1 s. during internal erase operation, any attempt to read dq 7 will produce a ?0?. once the internal erase operation is completed, dq 7 will produce a ?1?. the data# polling is valid after the rising edge of fourth we# (or ce#) pulse for program operation. for sector-, block- or chip-erase, the data# polling is valid after the rising edge of sixth we# (or ce#) pulse. see figure 8 for data# polling timing diagram and figure 22 for a flowchart. toggle bits (dq6 and dq2) during the internal program or erase operation, any consecutive attempts to read dq 6 will produce alternating ?1?s and ?0?s, i.e., toggling between 1 and 0. when the internal program or erase operation is completed, the dq 6 bit will stop toggling. the device is then ready for the next operation. for sector- , block-, or chip-erase, the toggle bit (dq 6 ) is valid after the rising edge of sixth we# (or ce#) pulse. dq 6 will be set to ?1? if a read operation is attempted on an erase-suspended sector/block. if pro- gram operation is initiated in a sector/block not selected in erase-suspend mode, dq 6 will toggle. an additional toggle bit is available on dq 2 , which can be used in conjunction with dq 6 to check whether a particular sector is being actively erased or erase-suspended. table 3 shows detailed status bits information. the toggle bit (dq 2 ) is valid after the rising edge of the last we# (or ce#) pulse of write operation. see figure 9 for toggle bit timing diagram and figure 22 for a flowchart. note: dq 7 ,dq 6 and dq 2 require a valid address when reading status information. table 3: write operation status status dq 7 dq 6 dq 2 ry/by# normal operation standard program dq 7 # toggle no toggle 0 standard erase 0 toggle toggle 0 erase-suspend mode read from erase-sus- pended sector/block 1 1 toggle 1 read from non- erase- suspended sector/block data data data 1 program dq 7 # toggle n/a 0 t3.0 25020
?2011 silicon storage technology, inc. ds25020a 06/11 11 32 mbit multi-purpose flash plus SST39VF3201C / sst39vf3202c preliminary specifications a microchip technology company ready/busy# (ry/by#) the devices include a ready/busy# (ry/by#) output signal. ry/by# is an open drain output pin that indicates whether an erase or program operation is in progress. since ry/by# is an open drain out- put, it allows several devices to be tied in parallel to v dd via an external pull-up resistor. after the rising edge of the final we# pulse in the command sequence, the ry/by# status is valid. when ry/by# is actively pulled low, it indicates that an erase or program operation is in progress. when ry/by# is high (ready), the devices may be read or left in standby mode. data protection the SST39VF3201C/3202c pro vide both hardware and software features to protect nonvolatile data from inadvertent writes. hardware data protection noise/glitch protection: a we# or ce# pulse of less than 5 ns will not initiate a write cycle. v dd p o w er up/do wn detection: the write operation is inhibited when v dd is less than 1.5v. wr ite inhibit mode: forcing oe# low, ce# high, or we# high will inhibit the write operation. this pre- vents inadvertent writes during power-up or power-down. hardware block protection the sst39vf3202c support top hardware block protection, which protects the top two 4-kword blocks of the device. the SST39VF3201C support bottom hardware block protection, which protects the bottom two 4-kword blocks of the device. the boot block address ranges are described in table 4. program and erase operations are prevented on the two 4-kword blocks when wp# is low. if wp# is left floating, it is internally held high via a pull-up resistor, and the boot block is unprotected, enabling program and erase operations on that block. hardware reset (rst#) the rst# pin provides a hardware method of resetting the device to read array data. when the rst# pin is held low for at least t rp, any in-progress operation will terminate and return to read mode. when no internal program/erase operation is in progress, a minimum period of t rhr is required after rst# is driven high before a valid read can take place. see figure 17. the erase or program operation that has been interrupted needs to be re-initiated after the device resumes normal operation mode to ensure data integrity. table 4: boot block address ranges product address range bottom boot block SST39VF3201C 000000h-001fffh top boot block sst39vf3202c 1fe000h-1fffffh t4.0 25020
?2011 silicon storage technology, inc. ds25020a 06/11 12 32 mbit multi-purpose flash plus SST39VF3201C / sst39vf3202c preliminary specifications a microchip technology company software data protection (sdp) the SST39VF3201C/3202c pro vide the jedec approved software data protection scheme for all data alteration operations, i.e., program and erase. any program operation requires the inclusion of the three-byte sequence. the three-byte load sequence is used to initiate the program operation, provid- ing optimal protection from inadvertent write operations, e.g., during the system power-up or power- down. any erase operation requires the inclusion of six-byte sequence. these devices are shipped with the software data protection permanently enabled. see table 7 for the specific software com- mand codes. during sdp command sequence, invalid commands will abort the device to read mode within t rc. the contents of dq 15 -dq 8 can be v il or v ih , but no other value, during any sdp command sequence. common flash memory interface (cfi) the SST39VF3201C/3202c also contain the cfi information to describe the characteristics of the device. in order to enter the cfi query mode, the system must write the three-byte sequence, same as product id entry command with 98h (cfi query command) to address 555h in the last byte sequence. the system can also enter the cfi query mode, by using the one-byte sequence with 55h on address and 98h on data bus. once the device enters the cfi query mode, the system can read cfi data at the addresses given in tables 8 through 10. the system must write the cfi exit command to return to read mode from the cfi query mode. product identification the product identification mode identifies the devices as the SST39VF3201Cand sst39vf3202c , and the manufacturer as sst. this mode may be accessed through software operations. users may use the software product identification operation to identify the part (i.e., using the device id) when using multiple manufacturers in the same socket. for details, see table 7 for software operation, figure 13 for the software id entry and read timing diagram and figure 23 for the software id entry command sequence flowchart. product identification mode exit/cfi mode exit in order to return to the standard read mode, the software product identification mode must be exited. exit is accomplished by issuing the software id exit command sequence, which returns the device to the read mode. this command may also be used to reset the device to the read mode after any inad- vertent transient condition that apparently causes the device to behave abnormally, e.g., not read cor- rectly. please note that the software id exit/cfi exit command is ignored during an internal program or erase operation. see t able 7 for software command codes, figure 15 for timing waveform, and fig- ure 23 and figure 24 for flowcharts. table 5: product identification address data manufacturer?s id 0000h bfh device id SST39VF3201C 0001h 235f sst39vf3202c 0001h 235e t5.0 25020
?2011 silicon storage technology, inc. ds25020a 06/11 13 32 mbit multi-purpose flash plus SST39VF3201C / sst39vf3202c preliminary specifications a microchip technology company security id the SST39VF3201C/3202c de vices offer a 136 word security id space. the secure id space is divided into two segments - one factory programmed segment and one user programmed segment. the first segment is programmed and locked at sst with a random 128-bit number. the 128-word user segment is left un-programmed for the customer to program as desired. to program the user segment of the security id, the user must use the security id word-program command. to detect end-of-write for the sec id, read the toggle bits. do not use data# polling. once this is complete, the sec id should be locked using the user sec id program lock-out. this disables any future corruption of this space. note that regardless of whether or not the sec id is locked, neither sec id segment can be erased. the secure id space can be queried by executing a three-byte command sequence with enter sec id command (88h) at address 555h in the last byte sequence. to exit this mode, the exit sec id com- mand should be executed. refer to t able 7 for more details.
?2011 silicon storage technology, inc. ds25020a 06/11 14 32 mbit multi-purpose flash plus SST39VF3201C / sst39vf3202c preliminary specifications a microchip technology company operations table 6: operation modes selection mode ce# oe# we# dq address read v il v il v ih d out a in program v il v ih v il d in a in erase v il v ih v il x 1 1. x can be v il or v ih , but no other value. sector or block address, xxh for chip-erase standby v ih x x high z x write inhibit x v il x high z/ d out x xxv ih high z/ d out x product identification software mode v il v il v ih see table 7 t6.0 25020 table 7: software command sequence command sequence 1st bus write cycle 2nd bus write cycle 3rd bus write cycle 4th bus write cycle 5th bus write cycle 6th bus write cycle addr 1 1. address format a 10 -a 0 (hex). addresses a 11 -a 20 can be v il or v ih, but no other value, for command sequence for SST39VF3201C/3202c. data 2 2. dq 15 -dq 8 can be v il or v ih , but no other value, for command sequence addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 word-program 555h aah 2aah 55h 555h a0h wa 3 3. wa = program word address data sector-erase 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h sa x 4 4. sa x for sector-erase; uses a ms -a 11 address lines ba x , for block-erase; uses a ms -a 15 address lines a ms = most significant address a ms =a 20 for SST39VF3201C/3202c 50h block-erase 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h ba x 4 30h chip-erase 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h erase-suspend xxxxh b0h erase-resume xxxxh 30h query sec id 5 555h aah 2aah 55h 555h 88h user security id word-program 555h aah 2aah 55h 555h a5h wa 6 data user security id program lock-out 555h aah 2aah 55h 555h 85h xxh 6 0000h software id entry 7,8 555h aah 2aah 55h 555h 90h cfi query entry 555h aah 2aah 55h 555h 98h cfi query entry 55h 98h software id exit 9,10 /cfi exit/sec id exit 555h aah 2aah 55h 555h f0h software id exit 9,10 /cfi exit/sec id exit xxh f0h t7.0 25020
?2011 silicon storage technology, inc. ds25020a 06/11 15 32 mbit multi-purpose flash plus SST39VF3201C / sst39vf3202c preliminary specifications a microchip technology company 5. with a ms -a 4 = 0; sec id is read with a 3 -a 0 , sst id is read with a 3 = 0 (address range = 000000h to 000007h), user id is read with a 3 = 1 (address range = 000008h to 000087h). lock status is read with a 7 -a 0 = 0000ffh. unlocked: dq 3 = 1 / locked: dq 3 =0. 6. valid word-addresses for sec id are from 000000h-000007h and 000008h to 000087h. 7. the device does not remain in software product id mode if powered down. 8. for manufacture id with a ms -a 0 =0;sst manufacturer id = 00bfh is read for device id - device id can be read either in one cycle (address 01h) or in three cycles (addresses 01h, 0eh and 0fh) one-cycle method - with a ms -a 1 =0, a 0 =1; SST39VF3201C/3202c device id = 235f/235e is read three-cycle method - with a ms -a 1 =0, a 0 =1; SST39VF3201C/3202c device id = 235f/235e is read (cycle 1) with a ms -a 4 =0; a 3 -a 1 =1; a 0 =0; SST39VF3201C/3202c device id additional info = 1a/1a is read (note: 1a = 32 mbit) (cycle 2) with a ms -a 4 =0; a 3 -a 0 =1; SST39VF3201C/3202c device id additional info = 00/01 is read (00/01 = bottom/top boot) (cycle 3) a ms = most significant address a ms =a 20 for SST39VF3201C/3202c 9. both software id exit operations are equivalent 10. if users never lock after programming, sec id can be programmed over the previously unprogrammed bits (data=1) using the sec id mode again (the programmed ?0? bits cannot be reversed to ?1?). valid word-addresses for sec id are from 000000h-000007h and 000008h to 000087h. table 8: cfi query identification string 1 for SST39VF3201C/3202c 1. refer to cfi publication 100 for more details. address data data 10h 0051h query unique ascii string ?qry? 11h 0052h 12h 0059h 13h 0002h primary oem command set 14h 0000h 15h 0000h address for primary extended table 16h 0000h 17h 0000h alternate oem command set (00h = none exists) 18h 0000h 19h 0000h address for alternate oem extended table (00h = none exits) 1ah 0000h t8.0 25020
?2011 silicon storage technology, inc. ds25020a 06/11 16 32 mbit multi-purpose flash plus SST39VF3201C / sst39vf3202c preliminary specifications a microchip technology company table 9: system interface information for SST39VF3201C/3202c address data data 1bh 0027h v dd min (program/erase) dq 7 -dq 4 : volts, dq 3 -dq 0 : 100 millivolts 1ch 0036h v dd max (program/erase) dq 7 -dq 4 : volts, dq 3 -dq 0 : 100 millivolts 1dh 0000h v pp min. (00h = no v pp pin) 1eh 0000h v pp max. (00h = no v pp pin) 1fh 0003h typical time out for word-program 2 n s (2 3 = 8 s) 20h 0000h typical time out for min. size buffer program 2 n s (00h = not supported) 21h 0004h typical time out for individual sector/block-erase 2 n ms (2 4 =16ms) 22h 0005h typical time out for chip-erase 2 n ms (2 5 =32ms) 23h 0001h maximum time out for word-program 2 n times typical (2 1 x2 3 =16s) 24h 0000h maximum time out for buffer program 2 n times typical 25h 0001h maximum time out for individual sector/block-erase 2 n times typical (2 1 x2 4 =32ms) 26h 0001h maximum time out for chip-erase 2 n times typical (2 1 x2 5 =64ms) t9.0 25020 table 10: device geometry information for SST39VF3201C/3202c address data data 27h 0016h device size = 2 n bytes (16h = 22; 2 22 = 4mbyte) 28h 0001h flash device interface description; 0001h = x16-only asynchronous interface 29h 0000h 2ah 0000h maximum number of bytes in multi-byte write = 2 n (00h = not supported) 2bh 0000h 2ch 0003h number of erase sector/block sizes supported by device 2dh 0007h erase block1 region information. 2eh 0000h 2fh 0020h 30h 0000h 31h 003eh erase block2 region information. 32h 0000h 33h 0000h 34h 0001h 35h 0000h erase block3 region information. 36h 0000h 37h 0000h 38h 0000h 39h 0000h erase block4 region information. 3ah 0000h 3bh 0000h 3ch 0000h t10.0 25020
?2011 silicon storage technology, inc. ds25020a 06/11 17 32 mbit multi-purpose flash plus SST39VF3201C / sst39vf3202c preliminary specifications a microchip technology company absolute maximum stress ratings (applied conditions greater than those listed under ?absolute maximum stress ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. exposure to absolute maximum stress rating con- ditions may affect device reliability.) temperature under bias ............................................. -55c to +125c storage temperature ................................................ -65c to +150c d. c. voltage on any pin to ground potential ............................ -0.5v to v dd +0.5v transient voltage (<20 ns) on any pin to ground potential .................. -2.0v to v dd +2.0v voltage on a 9 pin to ground potential ..................................... -0.5v to 13.2v package power dissipation capability (t a = 25c) .................................. 1.0w surface mount solder reflow temperature ........................... 260c for 10 seconds output short circuit current 1 .................................................. 50ma 1. outputs shorted for no more than one second. no more than one output shorted at a time. table 11: operating range range ambient temp v dd commercial 0c to +70c 2.7-3.6v industrial -40c to +85c 2.7-3.6v t11.1 25020 table 12: ac conditions of test 1 1. see figures 19 and 20 input rise/fall time output load 5ns c l =30pf t12.1 25020
?2011 silicon storage technology, inc. ds25020a 06/11 18 32 mbit multi-purpose flash plus SST39VF3201C / sst39vf3202c preliminary specifications a microchip technology company power up specifications all functionalities and dc specifications are specified for a v dd ramp rate of greater than 1v per 100 ms (0v to 3v in less than 300 ms). if the vdd ramp rate is slower than 1v per 100 ms, a hardware reset is required. the recommended v dd power-up to reset# high time should be greater than 100 s to ensure a proper reset. figure 4: power-up diagram table 13: dc operating characteristics v dd = 2.7-3.6v 1 1. typical conditions for the active current shown on the front page of the data sheet are average values at 25c (room temperature), and v dd = 3v. not 100% tested. symbol parameter limits test conditions min max units i dd power supply current address input=v ilt /v iht 2 , at f=5 mhz, v dd =v dd max 2. see figure 19 read 3 3. the i dd current listed is typically less than 2ma/mhz, with oe# at v ih. typical v dd is 3v. 15 ma ce#=v il , oe#=we#=v ih , all i/os open program and erase 45 ma ce#=we#=v il , oe#=v ih i sb standby v dd current 50 a ce#=v ihc ,v dd =v dd max i alp auto low power 50 a ce#=v ilc ,v dd =v dd max all inputs=v ss or v dd, we#=v ihc i li input leakage current 1 a v in =gnd to v dd ,v dd =v dd max i liw input leakage current on wp# pin and rst# 10 a wp#=gnd to v dd or rst#=gnd to v dd i lo output leakage current 1 a v out =gnd to v dd ,v dd =v dd max v il input low voltage 0.8 v v dd =v dd min v ilc input low voltage (cmos) 0.3 v v dd =v dd max v ih input high voltage 0.7v dd vv dd =v dd max v ihc input high voltage (cmos) v dd -0.3 v v dd =v dd max v ol output low voltage 0.2 v i ol =100 a, v dd =v dd min v oh output high voltage v dd -0.2 v i oh =-100 a, v dd =v dd min t13.0 25020 1410 f24.0 v dd reset# ce# t pu-read 10 0 s v dd min 0v v ih t rhr 50 ns
?2011 silicon storage technology, inc. ds25020a 06/11 19 32 mbit multi-purpose flash plus SST39VF3201C / sst39vf3202c preliminary specifications a microchip technology company table 14: recommended system power-up timings symbol parameter minimum units t pu-read 1 1. this parameter is measured only for initial qualification and after a design or process change that could affect this parameter. power-up to read operation 100 s t pu-write 1 power-up to program/erase operation 100 s t14.0 25020 table 15: capacitance (ta = 25c, f=1 mhz, other pins open) parameter description test condition maximum c i/o 1 1. this parameter is measured only for initial qualification and after a design or process change that could affect this parameter. i/o pin capacitance v i/o =0v 10pf c in 1 input capacitance v in =0v 10pf t15.0 25020 table 16: reliability characteristics symbol parameter minimum specification units test method n end 1,2 1. this parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 2. n end endurance rating is qualified as a 10,000 cycle minimum for the whole device. a sector- or block-level rating would result in a higher minimum specification. endurance 10,000 cycles jedec standard a117 t dr 1 data retention 100 years jedec standard a103 i lth 1 latch up 100 + i dd ma jedec standard 78 t16.0 25020
?2011 silicon storage technology, inc. ds25020a 06/11 20 32 mbit multi-purpose flash plus SST39VF3201C / sst39vf3202c preliminary specifications a microchip technology company ac characteristics table 17: read cycle timing parameters v dd = 2.7-3.6v symbol parameter min max units t rc read cycle time 70 ns t ce chip enable access time 70 ns t aa address access time 70 ns t oe output enable access time 35 ns t clz 1 1. this parameter is measured only for initial qualification and after a design or process change that could affect this parameter. ce# low to active output 0 ns t olz 1 oe# low to active output 0 ns t chz 1 ce# high to high-z output 16 ns t ohz 1 oe# high to high-z output 16 ns t oh 1 output hold from address change 0 ns t rp 1 rst# pulse width 500 ns t rhr 1 rst# high before read 50 ns t ry 1,2 2. this parameter applies to sector-erase, block-erase, and program operations. this parameter does not apply to chip-erase operations. rst# pin low to read mode 20 s t17.0 25020 table 18: program/erase cycle timing parameters symbol parameter min max units t bp word-program time 10 s t as address setup time 0 ns t ah address hold time 30 ns t cs we# and ce# setup time 0 ns t ch we# and ce# hold time 0 ns t oes oe# high setup time 0 ns t oeh oe# high hold time 10 ns t cp ce# pulse width 40 ns t wp we# pulse width 40 ns t wph 1 1. this parameter is measured only for initial qualification and after a design or process change that could affect this parameter. we# pulse width high 30 ns t cph 1 ce# pulse width high 30 ns t ds data setup time 30 ns t dh 1 data hold time 0 ns t ida 1 software id access and exit time 150 ns t se sector-erase 25 ms t be block-erase 25 ms t sce chip-erase 50 ms t by 1,2 2. this parameter applies to sector-erase, block-erase, and program operations. ry/by# delay time 90 ns t br 1 bus recovery time 0 s t18.0 25020
?2011 silicon storage technology, inc. ds25020a 06/11 21 32 mbit multi-purpose flash plus SST39VF3201C / sst39vf3202c preliminary specifications a microchip technology company figure 5: read cycle timing diagram figure 6: we# controlled program cycle timing diagram 1410 f03.0 address a ms-0 dq 15-0 we# oe# ce# t ce t rc t aa t oe t olz v ih high-z t clz t oh t chz high-z data valid data valid t ohz note: a ms = most significant address a ms =a 20 for SST39VF3201C/3202c 1410 f04.0 addresses dq 15-0 ce# 555 2aa 555 addr xxaa xx55 xxa0 data word (addr/data) oe# we# ry/by# valid t dh t wph t as t ch t cs t ah t wp t ds t by t br t bp note: wp# must be held in proper logic state (v il or v ih ) 1s prior to and 1s after the command sequence. x can be v il or v ih , but no other value.
?2011 silicon storage technology, inc. ds25020a 06/11 22 32 mbit multi-purpose flash plus SST39VF3201C / sst39vf3202c preliminary specifications a microchip technology company figure 7: ce# controlled program cycle timing diagram figure 8: data# polling timing diagram 1410 f05.0 addresses dq 15-0 ce# 555 2aa 555 addr xxaa xx55 xxa0 data word (addr/data) oe# we# ry/by# valid t dh t cph t as t ch t cs t ah t cp t ds t by t br t bp note: wp# must be held in proper logic state (v il or v ih ) 1s prior to and 1s after the command sequence. x can be v il or v ih , but no other value. 1410 f06.0 address a 19-0- a ms-0 dq 7 data we# oe# ce# ry/by# data # data # data t oes t oeh t by t ce t oe note: a ms = most significant address a ms =a 20 for SST39VF3201C/3202c
?2011 silicon storage technology, inc. ds25020a 06/11 23 32 mbit multi-purpose flash plus SST39VF3201C / sst39vf3202c preliminary specifications a microchip technology company figure 9: toggle bits timing diagram figure 10: we# controlled chip-erase timing diagram 1410 f07.0 address a ms-0 dq 6 and dq 2 we# oe# ce# t oe t oeh t ce t oes two read cycles with same outputs note: a ms = most significant address a ms =a 20 for SST39VF3201C/3202c 1410 f08.0 addresses dq 15-0 we# 555 2aa 2aa 555 555 xx55 xx10 xx55 xxaa xx80 xxaa 555 oe# ce# ry/by# valid six-byte code for chip-erase t oeh t sce t by t br note: this device also supports ce# controlled chip-erase operation the we# and ce# signals are interchangeable as long as minimum timings are met. (see table 18) wp# must be held in proper logic state (v il or v ih ) 1 s prior to and 1 s after the command sequence. x can be v il or v ih, but no other value.
?2011 silicon storage technology, inc. ds25020a 06/11 24 32 mbit multi-purpose flash plus SST39VF3201C / sst39vf3202c preliminary specifications a microchip technology company figure 11: we# controlled block-erase timing diagram figure 12: we# controlled sector-erase timing diagram 1410 f09.0 addresses dq 15-0 we# 555 2aa 2aa 555 555 xx55 xx30 xx55 xxaa xx80 xxaa ba x oe# ce# ry/by# valid six-byte code for block-erase t wp t be t by t br note: this device also supports ce# controlled block-erase operation. the we# and ce# signals are inter- changeable as long as minimum timings are met. (see table 18). ba x = block address wp# must be held in proper logic state (v il or v ih ) 1s prior to and 1s after the command sequence. x can be v il or v ih , but no other value. 1410 f10.0 addresses dq 15-0 we# 555 2aa 2aa 555 555 xx55 xx50 xx55 xxaa xx80 xxaa sa x oe# ce# ry/by# valid six-byte code for sector-erase t wp t se t by t br note: this device also supports ce# controlled sector-erase operation. the we# and ce# signals are inter- changeable as long as minimum timings are met. (see table 18). sa x = block address wp# must be held in proper logic state (v il or v ih ) 1s prior to and 1s after the command sequence. x can be v il or v ih , but no other value.
?2011 silicon storage technology, inc. ds25020a 06/11 25 32 mbit multi-purpose flash plus SST39VF3201C / sst39vf3202c preliminary specifications a microchip technology company figure 13: software id entry and read figure 14: cfi query entry and read 1410 f11.0 address t ida dq 15-0 we# sw0 sw1 sw2 555 2aa 555 0000 0001 oe# ce# three-byte sequence for software id entry t wp t wph t aa 00bf device id xx55 xxaa xx90 note: device id = 235e for SST39VF3201Cand 235e for sst39vf3202c wp# must be held in proper logic state (v il or v ih ) 1 s prior to and 1 s after the command sequence. x can be v il or v ih, but no other value. 1410 f12.0 address t ida dq 15-0 we# sw0 sw1 sw2 555 2aa 555 oe# ce# three-byte sequence for cfi query entry t wp t wph t aa xx55 xxaa xx98 note: wp# must be held in proper logic state (v il or v ih ) 1 s prior to and 1 s after the command sequence. x can be v il or v ih, but no other value.
?2011 silicon storage technology, inc. ds25020a 06/11 26 32 mbit multi-purpose flash plus SST39VF3201C / sst39vf3202c preliminary specifications a microchip technology company figure 15: software id exit/cfi exit figure 16: secidentry 1410 f13.0 address a 14-0 dq 15-0 t ida t wp t whp we# sw0 sw1 sw2 555 2aa 555 three-byte sequence for software id exit and reset oe# ce# xxaa xx55 xxf0 note: wp# must be held in proper logic state (v il or v ih ) 1 s prior to and 1 s after the command sequence. x can be v il or v ih, but no other value. 1410 f14.0 address a ms-0 t ida dq 15-0 we# sw0 sw1 sw2 555 2aa 555 oe# ce# three-byte sequence for cfi query entry t wp t wph t aa xx55 xxaa xx88 note: a ms = most significant address a ms =a 20 for SST39VF3201C/3202c wp# must be held in proper logic state (v il or v ih ) 1 s prior to and 1 s after the command sequence. x can be v il or v ih, but no other value.
?2011 silicon storage technology, inc. ds25020a 06/11 27 32 mbit multi-purpose flash plus SST39VF3201C / sst39vf3202c preliminary specifications a microchip technology company figure 17: rst# timing diagram (when no internal operation is in progress) figure 18: rst# timing diagram (during program or erase operation) 1410 f15.0 ry/by# 0v rst# ce#/oe# t rp t rhr 1410 f16.0 ry/by# ce# oe# t rp t ry t br rst#
?2011 silicon storage technology, inc. ds25020a 06/11 28 32 mbit multi-purpose flash plus SST39VF3201C / sst39vf3202c preliminary specifications a microchip technology company figure 19: ac input/output reference waveforms figure 20: a test load example 1410 f17.0 reference points output input v it v iht v ilt v ot ac test inputs are driven at v iht (0.9 v dd ) for a logic ?1? and v ilt (0.1 v dd ) for a logic ?0?. measure- ment reference points for inputs and outputs are v it (0.5 v dd ) and v ot (0.5 v dd ). input rise and fall times (10% ? 90%) are <5 ns. note: v it -v input test v ot -v output test v iht -v input high test v ilt -v input low test 1410 f18.0 to tester to dut c l
?2011 silicon storage technology, inc. ds25020a 06/11 29 32 mbit multi-purpose flash plus SST39VF3201C / sst39vf3202c preliminary specifications a microchip technology company figure 21: word-program algorithm 1410 f19.0 start load data: xxaah address: 555h load data: xx55h address: 2aah load data: xxa0h address: 555h load word address/word data wait for end of program (t bp , data# polling bit, or toggle bit operation) program completed x can be v il or v ih , but no other value
?2011 silicon storage technology, inc. ds25020a 06/11 30 32 mbit multi-purpose flash plus SST39VF3201C / sst39vf3202c preliminary specifications a microchip technology company figure 22: wait options 1410 f20.0 wait t bp , t sce, t se or t be program/erase initiated internal timer toggle bit ye s ye s no no program/erase completed does dq 6 match read same word data# polling program/erase completed program/erase completed read word is dq 7 = true data read dq 7 program/erase initiated program/erase initiated ye s no ry/by# is ry/by# = 1 read ry/by# program/erase initiated program/erase completed
?2011 silicon storage technology, inc. ds25020a 06/11 31 32 mbit multi-purpose flash plus SST39VF3201C / sst39vf3202c preliminary specifications a microchip technology company figure 23: software id/cfi entry command flowcharts 1410 f21.0 load data: xxaah address: 555h software product id entry command sequence load data: xx55h address: 2aah load data: xx90h address: 555h wait t ida read software id load data: xxaah address: 555h cfi query entry command sequence load data: xx55h address: 2aah load data: xx98h address: 555h wait t ida read cfi data load data: xxaah address: 555h sec id query entry command sequence load data: xx55h address: 2aah load data: xx88h address: 555h wait t ida read sec id x can be v il or v ih , but no other value load data: xx98h address: 55h wait t ida read cfi data
?2011 silicon storage technology, inc. ds25020a 06/11 32 32 mbit multi-purpose flash plus SST39VF3201C / sst39vf3202c preliminary specifications a microchip technology company figure 24: software id/cfi exit command flowcharts 1410 f22.0 load data: xxaah address: 555h software id exit/cfi exit/sec id exit command sequence load data: xx55h address: 2aah load data: xxf0h address: 555h load data: xxf0h address: xxh return to normal operation wait t ida wait t ida return to normal operation x can be v il or v ih , but no other value
?2011 silicon storage technology, inc. ds25020a 06/11 33 32 mbit multi-purpose flash plus SST39VF3201C / sst39vf3202c preliminary specifications a microchip technology company figure 25: erase command sequence 1410 f23.0 load data: xxaah address: 555h chip-erase command sequence load data: xx55h address: 2aah load data: xx80h address: 555h load data: xx55h address: 2aah load data: xx10h address: 555h load data: xxaah address: 555h wait t sce chip erased to ffffh load data: xxaah address: 555h sector-erase command sequence load data: xx55h address: 2aah load data: xx80h address: 555h load data: xx55h address: 2aah load data: xx50h address: sa x load data: xxaah address: 555h wait t se sector erased to ffffh load data: xxaah address: 555h block-erase command sequence load data: xx55h address: 2aah load data: xx80h address: 555h load data: xx55h address: 2aah load data: xx30h address: ba x load data: xxaah address: 555h wait t be block erased to ffffh x can be v il or v ih , but no other value
?2011 silicon storage technology, inc. ds25020a 06/11 34 32 mbit multi-purpose flash plus SST39VF3201C / sst39vf3202c preliminary specifications a microchip technology company product ordering information valid combinations for SST39VF3201C valid combinations for sst39vf3202c note: valid combinations are those products in mass production or will be in mass production. consult your sst sales representative to confirm availability of valid combinations and to determine availability of new combi- nations. SST39VF3201C-70-4i-eke SST39VF3201C-70-4i-b3ke SST39VF3201C-70-4c-eke SST39VF3201C-70-4c-b3ke sst39vf3202c-70-4i-eke sst39vf3202c-70-4i-b3ke sst39vf3202c-70-4c-eke sst39vf3202c-70-4c-b3ke sst 39 vf 3201c - 70 - 4i - eke xx xx xxxxx - xx - xx - xxx environmental attribute e 1 = non-pb package modifier k = 48 balls or leads package type e = tsop (type1, die up, 12mm x 20mm) b3 = tfbga (6mm x 8mm, 0.8mm pitch) temperature range c = commercial = 0c to +70c i = industrial = -40c to +85c minimum endurance 4 = 10,000 cycles read access speed 70 = 70 ns hardware block protection 1 = bottom boot-block 2 = top boot-block device density 320= 32mbit voltage v = 2.7-3.6v product series 39 = multi-purpose flash plus 1. environmental suffix ?e? denotes non-pb solder. sst non-pb solder devices are ?rohs compliant?.
?2011 silicon storage technology, inc. ds25020a 06/11 35 32 mbit multi-purpose flash plus SST39VF3201C / sst39vf3202c preliminary specifications a microchip technology company packaging diagrams figure 26: 48-lead thin small outline package (tsop) 12mm x 20mm, sst package code: ek 1.05 0.95 0.70 0.50 18.50 18.30 20.20 19.80 0.70 0.50 12.20 11.80 0.27 0.17 0.15 0.05 48-tsop-ek-8 note: 1. complies with jedec publication 95 mo-142 dd dimensions, although some dimensions may be more stringent. 2. all linear dimensions are in millimeters (max/min). 3. coplanarity: 0.1 mm 4. maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads. 1.20 max. 1mm 0- 5 detail pin # 1 identifier 0.50 bsc
?2011 silicon storage technology, inc. ds25020a 06/11 36 32 mbit multi-purpose flash plus SST39VF3201C / sst39vf3202c preliminary specifications a microchip technology company figure 27: 48-ball thin-profile, fine-pitch ball grid array (tfbga) 6mm x 8mm, sst package code: b3k a1 corner hgfedcba abcdefgh bottom view top view side view 6 5 4 3 2 1 6 5 4 3 2 1 seating plane 0.35 0.05 1.10 0.10 0.12 6.00 0.10 0.45 0.05 (48x) a1 corner 8.00 0.10 0.80 4.00 0.80 5.60 48-tfbga-b3k-6x8-450mic-5 note: 1. complies with jedec publication 95, mo-210, variant ab-1 , although some dimensions may be more stringent. 2. all linear dimensions are in millimeters. 3. coplanarity: 0.12 mm 4. ball opening size is 0.38 mm ( 0.05 mm) 1mm
?2011 silicon storage technology, inc. ds25020a 06/11 37 32 mbit multi-purpose flash plus SST39VF3201C / sst39vf3202c preliminary specifications a microchip technology company table 19: revision history number description date 00 ? initial release nov 2009 01 ? revised i sb and i alp in table 13 on page 19 aug 2010 a ? applied new document format ? released document under letter revision system ? updated spec number from s71410 to ds25020 jun 2011 ? 2011 silicon storage technology, inc?a microchip technology company. all rights reserved. sst, silicon storage technology, the sst logo, superflash, mtp, and flashflex are registered trademarks of silicon storage tech- nology, inc. mpf, sqi, serial quad i/o, and z-scale are trademarks of silicon storage technology, inc. all other trademarks and registered trademarks mentioned herein are the property of their respective owners. specifications are subject to change without notice. refer to www.microchip.com for the most recent documentation. for the most current package drawings, please see the packaging specification located at http://www.microchip.com/packaging. memory sizes denote raw storage capacity; actual usable capacity may be less. sst makes no warranty for the use of its products other than those expressly contained in the standard terms and conditions of sale. for sales office(s) location and information, please see www.microchip.com. silicon storage technology, inc. a microchip technology company www.microchip.com isbn:978-1-61341-239-8

▲Up To Search▲

Price & Availability of SST39VF3201C

	To Download SST39VF3201C Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .